Multilayer printed wiring board for semiconductor devices and method for manufacturing the board

ABSTRACT

A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

BACKGROUND OF THE INVENTION

The present application is a divisional of and claims the benefit ofpriority to U.S. application Ser. No. 11/555,881, filed Nov. 2, 2006,which claims the benefit of priority to Japanese Patent Application No.2005-319432, filed Nov. 2, 2005. The contents of those applications areincorporated herein by reference in their entireties.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multilayer printed wiring board forsemiconductor devices and methods for a manufacturing such board.

2. Description of the Related Art

Japanese Laid-Open Publication No. 2000-323613 (Date of Laid-Open: Nov.24, 2000) (corresponding to US Patent Application Publication No. US2002/0195272 A1; Pub. Date Dec. 26, 2002) discloses a multilayer printedwiring board, having a small thickness, for semiconductor devices,wherein the multilayer printed wiring board is manufactured in such amanner that a copper plate serving as a support is prepared, asemiconductor device-mounting layer having a surface for mountingsemiconductor devices and an externally connecting layer having asurface for an external connection are formed on the copper plate;via-holes, conductive wires, and an insulating layer are formed in thatorder in the direction from the semiconductor device-mounting layer tothe externally connecting layer; and the copper plate is then removed.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a multilayer printedwiring board, has a a core layer having an opening, and a conductivefilm formed on an upper surface of the core layer and closing one end ofthe opening of the core layer, a via-hole formed in the opening of thecore layer, a first resin layer formed over the upper surface of thecore layer and having openings, a via-hole formed in the opening of theresin layer. The via-holes of the one or more resin layers are open inthe direction opposite to the direction in which the via-hole of thecore layer is open.

According to another aspect of the present invention, a method formanufacturing a multilayer printed wiring board, includes preparing asingle- or double-sided copper-clad laminate, and forming a conductivefilm on an upper surface of the copper-clad laminate, forming a resinlayer on the upper surface of the copper-clad laminate, forming aopening for a via-hole in the resin layer, forming the via-hole in theresin layer, forming a opening for via-hole in the copper-clad laminate,forming the via-hole in the copper-clad. The via-holes formed in theresin layer are open in the direction in which the via-hole formed inthe copper-clad laminate is open.

According to yet another aspect of the present invention, a corelessmultilayer printed wiring board, has a coreless layer having an opening,and a conductive film formed on an upper surface of the coreless layerand closing one end of the opening of the coreless layer, a via-holeformed in the opening of the coreless layer, a first resin layer formedon the coreless layer and the conductive film and having an openingreaching to the conductive film, a via-hole formed in the opening of thefirst resin layer, a second resin layer formed on the upper surface ofthe first resin layer and having an opening, a via-hole formed in theopening of the second resin layer. The via-holes formed in the first andsecond resin layers are open in the direction opposite to the directionin which the via-hole formed in the third resin layer is open.

According to yet another aspect of the present invention, a method formanufacturing a multilayer printed wiring board, includes preparing asupport plate, and forming a conductive film on the support plate,forming a first resin layer on the upper surface of the support plate,forming a first opening for a first via-hole in the first resin layer,forming the first via-hole in the first resin layer, forming a secondresin layer on the upper surface of the first resin layer, forming asecond opening for a second via-hole in the second resin layer, formingthe second via-hole in the second resin layer, removing the supportplate, forming a coreless layer on the lower surface of the first resinlayer, forming a third opening for a third via-hole in the corelesslayer, forming the third via-hole in the coreless layer. The via-holesformed in the first and second resin layers are open in the directionopposite to the direction in which the via-hole formed in the corelesslayer is open.

According to another aspect of the present invention, a multilayerprinted wiring board has an insulating layer having an opening, and aconductive film formed on a surface of the insulating layer and closingone end of the opening of the insulating layer, a resin layer formedover the insulating layer and the conductive film and having at leastone opening, a first via-hole structure formed in the opening in theinsulating layer and comprising an electroless plating film on a surfaceof the opening in the insulating layer and the conductive film and anelectroplating film formed on the electroless plating film, at least onevia-hole structure formed in the at least one opening of the resin layerand comprising an electroless plating film formed on a surface of theopening of the resin layer and an electroplating film formed on theelectroless plating film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a multilayer printed wiring boardaccording to a first embodiment of the present invention;

FIGS. 2A to 2R are illustrations showing steps of manufacturing themultilayer printed wiring board shown in FIG. 1;

FIG. 3 is a sectional view of a multilayer printed wiring boardaccording to a second embodiment of the present invention;

FIGS. 4A to 4T are illustrations showing steps of manufacturing themultilayer printed wiring board shown in FIG. 3; and

FIG. 5 is a sectional view of one embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will now be described in detailwith reference to the accompanying drawings. In order to avoidrepetition, the same components shown in the accompanying drawings shallhave the same reference numerals.

First Embodiment

FIG. 1 shows a multilayer printed wiring board 20 according to a firstembodiment of the present invention. The multilayer printed wiring board20 of the first embodiment includes a first resin layer 26-1, firstvia-holes 33-1 formed in the first resin layer 26-1, a second resinlayer 26-2 disposed on the upper surface of the first resin layer 26-1,second via-holes 33-2 formed in the second resin layer 26-2, a corelayer 22 disposed on the lower surface of the first resin layer 26-1,and third via-holes 42 formed in the core layer 22. The first and secondvia-holes 33-1 and 33-2 are open in the direction opposite to thedirection in which the third via-holes 42 are open.

The first and second via-holes 33-1 and 33-2 may broaden upward and maytaper downward. In contrast, the third via-holes 42 may taper upward andmay broaden downward.

The core layer 22, which is located lowermost, is preferably made offiber-reinforced plastics (FRP). The core layer 22 is more preferablyprepared from a copper-clad laminate such as a glass cloth base epoxyresin impregnated double-sided copper clad laminate.

The multilayer printed wiring board 20 of the first embodiment includesthe first and second resin layers 26-1 and 26-2 as shown in FIG. 1. Themultilayer printed wiring board 20 of the first embodiment is notlimited to such a configuration and may include one or more resin layersdisposed on the upper surface of the core layer 22.

-   (1) Since the first and second via-holes 33-1 and 33-2 are open in    the direction opposite to the direction in which the third via-holes    42 are open, the first and second resin layers 26-1 and 26-2 are    warped in the direction opposite to the direction in which the core    layer 22 are warped; hence, the multilayer printed wiring board 20    of the first embodiment is hardly warped.

Since the multilayer printed wiring board 20 of the first embodiment ishardly warped by heating during the reflow of solder bumps, the distancebetween the multilayer printed wiring board 20 of the first embodimentand each semiconductor element is maintained substantially constant.Therefore, even if the multilayer printed wiring board 20 of the firstembodiment has a semiconductor element-mounting region (that is, aregion having pads connected to electrodes of the semiconductorelements) having a large area of 200 to 2,000 mm² and the number of thepads is 2,000 to 30,000, problems such as misconnections hardly occur.

-   (2) Since the core layer 22 typically includes the glass-based    material, the core layer 22 has a smaller thermal expansion    coefficient and a higher dimensional stability as compared to a    layer made of only resin, for example, an epoxy resin. If    semiconductor elements (not shown) are mounted on the second resin    layer 26-2, the semiconductor elements, the second resin layer 26-2,    the first resin layer 26-1, and the core layer 22 are arranged in    that order. That is, the first and second resin layers 26-1 and 26-2    are sandwiched between the core layer 22 and the semiconductor    elements having a thermal expansion coefficient which is less than    those of the first and second resin layers 26-1 and 26-2. Therefore,    the multilayer printed wiring board 20 of the first embodiment may    reduce the occurrence of cracks during a temperature cycle test    because the multilayer printed wiring board 20 is hardly warped.-   (3) The core layer 22 is preferably prepared from the copper-clad    laminate and uses the copper foils 23 as described above. For    example, the core layer 22 is typically of a glass-cloth base    epoxy-resin impregnated copper-clad laminate. When a copper-clad    laminate is in general manufactured by a laminate maker, a surface    of each copper foil 23 facing to a laminate 22 is usually    matte-finished (roughened) such that the copper foil 23 is securely    fixed to the copper-clad laminate 22. The microscopic observation of    the copper foil 23 shows that the copper foil 23 has protrusions    (anchors) 27 extending into the copper-clad laminate 22 as shown in    the circles in FIG. 1. This allows the copper foil 23 to be tightly    fixed to the copper-clad laminate 22.

That is, the adhesion between the copper foil 23 and the copper-cladlaminate 22 is very strong. Hence, the multilayer printed wiring board20 of the first embodiment is tough.

-   (4) The core layer 22 is preferably prepared from a glass cloth base    epoxy-resin impregnated copper-clad laminate. The glass cloth base    includes a plurality of sheets of woven glass fabric (not shown)    with high dimensional stability against heat. Since the multilayer    printed wiring board 20 of the first embodiment has the sheets of    woven glass fabric, therefore it has high stiffness and is hardly    warped.

(Method for Manufacturing)

A method for manufacturing the multilayer printed wiring board 20 of thefirst embodiment will now be described with reference to FIGS. 2A to 2R.

As shown in FIG. 2A, a double-sided copper-clad laminate (for example,NEMA grade FR-4) 21 is prepared as starting material. The copper-cladlaminate 22 for a core layer is preferably formed in such a manner thatone sheet or two sheets (not shown) of woven glass fabric impregnatedwith a thermosetting epoxy resin is semi-cured. The copper-clad laminate21 is then formed by cladding copper foils to both surfaces of thecopper-clad laminate 22, respectively, and then these are heat-cured.For example, a glass cloth base epoxy-resin impregnated copper-cladlaminate with a thickness of about 0.06 mm, including the copper foils23 each having a thickness of about 12 μm may be used.

Alternatively, the following laminates may be used to manufacture thecore layer 22: a laminate including a glass-based material impregnatedwith a bismaleimide triazine resin, a laminate including a glass-basedmaterial impregnated with a polyphenylene ether resin, or a laminateincluding a glass-based material impregnated with a polyimide resin. Thecore layer 22 preferably has a thickness of 0.03 mm to 0.40 mm. Thethickness of the copper-clad laminate is more preferably is from 0.03 mmto 0.12 mm. This is because the warpage of the multilayer printed wiringboard 20 of the first embodiment can be reduced due to the stiffness ofthe core layer 22 and the counter balance between the warpage of thecore layer 22 and that of the first and second resin layers 26-1 and26-2.

As shown in FIG. 2B, first etching resist layers 24 are provided onregions of the upper one of the copper foils 23. The first etchingresist layers 24 may be formed in such a manner that, for example, a dryfilm is laminated on the upper copper foil 23 and then partly removed toform a conductive film by photolithography. Alternatively, the firstetching resist layers 24 may be formed by screen printing using a liquidresist.

As shown in FIG. 2C, portions of the upper copper foil 23 that areexposed from the first etching resist layers 24 are removed by etching.

As shown in FIG. 2D, the first etching resist layers 24, disposed on theremaining portions of the upper copper foil 23, are removed, whereby afirst conductive film 25 made of the upper copper foil 23 is formed. Theconductive film includes one or more of a land, a signal conductivecircuit, a power conductive circuit and/or a grand conductive circuit.The via-hole is formed on the land.

As shown in FIG. 2E, the first resin layer 26-1 is provided on the corelayer 22. The first resin layer 26-1 may be formed in such a manner thatan interlayer insulating resin film (for example, a film, grade ABF,available from Ajinomoto Fine-Techno. Co. Inc), a semi-cured resin sheetsuch as a prepreg and the like is attached to the core layer 22 and thenheat-cured, or in such a manner that pre-cured resin is applied to thecore layer 22 by screen printing and then heat-cured. A thickness of thefirst resin layer 26-1 may be from 0.02 mm to 0.06 mm. The thickness ofthe core layer may be equal to or thicker than the thickness of thefirst resin layer. Before the first resin layer 26-1 is formed, thesurfaces (including side surfaces) of the first conductive film 25 maybe roughened.

As shown in FIG. 2F, a first opening 26 a-1 for forming the firstvia-hole 33-1 is formed in the first resin layer 26-1 by laserirradiation using, for example, a carbon dioxide laser such that thefirst opening 26 a-1 is located above the respective conductive film 25on the core layer. Since the conductive film 25 on the core layerfunctions as a stopper during the formation of the first opening 26 a-1by laser irradiation, the first opening 26 a-1 reaches an upper surfaceof the conductive film 25 on the core layer. That is, the first via-hole33-1 extends from an upper surface of the first resin layer 26-1 to theupper surface of the conductive film 25 on the core layer. The firstopening 26 a-1 may taper toward conductive film 25 on the core layer,that is, the first opening 26 a-1 may have a downward tapered shape.Therefore, the first via-hole 33-1 may be, not rectangular,substantially trapezoidal in cross section.

An excimer laser, a YAG laser, or a UV laser may be used instead of thecarbon dioxide laser. A protective film such as a PET film may be usedduring the formation of the first openings 26 a-1 as required. This maybe applied to the formation of openings below.

As shown in FIG. 2G, catalyst seeds for electroless plating are providedon the first resin layer 26-1 having the first opening 26 a-1 and afirst copper layer (an electroless plating film) 28-1 with a thicknessof 0.6 to 3.0 μm is then formed on the first resin layer 26-1 byelectroless plating. Before the first copper layer 28-1 is formed, thefirst resin layer 26-1 may be processed desmear as required such thatresin residues are removed therefrom. Before the catalyst seeds forelectroless plating, a surface of the first resin layer may beroughened.

As shown in FIG. 2H, a second copper layer (an electroplating film) 30-1with a thickness of, for example, several ten micrometers is formed onthe first copper layer 28-1 by electroplating using the first copperlayer 28-1 as a feeder, that is, an electrode. Alternatively, the secondcopper layer 30-1 may be formed by electrolytic solder plating.Alternatively, the first copper layer 28-1 and the second copper layer30-1 may be entirely formed by electroless copper plating, then thesecond copper layer 30-1 may be flattened by an appropriate process asrequired.

As shown in FIG. 2I, second etching resist layers 32-1 are provided onthe second copper layer 30-1. For example, the second etching resistlayers 32-1 may be formed by photolithography or screen printing asdescribed above with reference to FIG. 2B.

As shown in FIG. 2J, regions of the first and second copper layers 28-1and 30-1 that are exposed from the second etching resist layers 32-1 areremoved by etching.

As shown in FIG. 2K, the second etching resist layers 32-1 on theremaining regions of the second copper layer 30-1 are removed, whereby asecond conductive film 34-1 made of the first and second copper layers28-1 and 30-1 is formed on the first resin layer 26-1. The secondconductive film 34-1 is formed by a subtractive process as describedabove and may be formed by a known semi-additive process. The secondconductive film includes one or more of a signal conductive circuit, apower conductive circuit, a grand conductive circuit and/or a land. Inthis step, the first via-hole 33-1 is formed such that the firstconductive film 25 is electrically connected to the respective secondconductive film 34-1. The first via-hole may be a filled via-hole whichis substantially filled the first opening with the electroplating film.The first via-hole 33-1 may have a cross-sectional shape correspondingto that of the first opening 26 a-1 described with reference to FIG. 2F,thus it may taper toward the conductive film on the core layer,therefore the first via-hole 33-1 has substantially an inversedfrusto-conical shape. The first via-hole has a bottom surface contactingthe conductive film 25 on the core layer, and the bottom surface has adiameter which is from 40 μm to 150 μm.

At the point of time when this step is finished, the second conductivefilm 34-1 is formed on the first resin layer 26-1 and the first via-hole33-1 is formed in the first resin layer. Therefore, a desired number ofresin layers may be formed on the first resin layer 26-1 by repeatingthe steps shown in FIGS. 2E to 2K. In this embodiment, these steps arerepeated one more time. The second via-hole 33-2 has a bottom surfacecontacting the conductive film on the first resin layer and the bottomsurface has a diameter which is from 40 μm to 150 μm.

As shown in FIG. 2L, the second resin layer 26-2 is formed on the firstresin layer 26-1 by repeating the steps shown in FIGS. 2E to 2K once. Athickness of the second resin layer 26-1 may be from 0.02 mm to 0.06 mm.The thickness of the second resin layer is equal to or thinner thanthickness of the core layer. A second opening in the second resin layerfor the second via-hole 33-2 may taper toward the second conductive film34-1. The second via-hole has a contacting surface contacting the secondconductive film 34-1 on the first resin layer and having a diameterwhich is from 40 μm to 150 μm.

As shown in FIG. 2M, a third opening 22 a for forming the third via-hole42 is formed in the core layer 22 in such a manner that the lower one ofthe copper foils 23 is partly removed by photolithography and regions ofthe lower surface of the core layer 22 exposed are then irradiated witha laser beam. This process is so-called a conformal process. In thisstep, the conductive film 25 functions as stopper, hence, the thirdopening 22 a reaches to the lower surface of the conductive film 25.Therefore, the third opening 22 a is open in the direction opposite tothe direction in which the first opening 26 a-1 in the first resin layer26-1 and the second opening 25 a-2 in the second resin layer 26-2 areopen. The third opening 22 a may taper toward the conductive film 25 onthe core layer, that is, the third opening 22 a may have an upwardtapered shape.

As shown in FIG. 2N, a third copper layer(an electroless plating film)37 is formed over the remaining regions of the lower copper foil 23 andthe core layer 22 having the third opening 22 a by electroless copperplating. Before the third copper layer 37 is formed, catalyst seeds forelectroless plating may be provided on the core layer 22 by, forexample, sputtering or plating as required.

As shown in FIG. 2O, plating resist layers 39 are provided on the thirdcopper layer 37. The plating resist layers 39 may be formed byphotolithography or screen printing as described above with reference toFIG. 2B.

As shown in FIG. 2P, a fourth copper layer(an electroplating film) 38 isformed on the third copper layer 37 by electroplating using the thirdcopper layer 37 as a feeder, whereby the third via-hole 42 is formed.The third via-hole 42 is open in the direction opposite to the directionin which the first via-hole 33-1 and second via-hole 33-2 shown in FIGS.2K and 2L are open. The third via-holes 42 may taper toward conductivefilm 25 on the core layer. The third via-hole may be a filled via-holewhich is filled the third opening substantially with the electroplatingfilm. The third and fourth copper layers 37 and 38 may be entirelyformed by electroless copper plating. The third via-hole has a bottomsurface contacting the conductive film 25 on the core layer and thebottom surface has a diameter which is from 60 μm to 250 μm. Thediameter of the bottom surface of the third via-hole is larger thanthose of the first and second via-holes.

As shown in FIG. 2Q, the plating resist layers 39 disposed on the thirdcopper layer 37 are removed.

As shown in FIG. 2R, the third copper layer 37 and the remaining regionsof the lower copper foil 23 are removed by etching. At this time,appropriate etching resist layers may be formed on the fourth copperlayers 37, a third conductive film 30-2 formed on the second resin layer26-2 and the second via-hole 33-2. These etching resist layers are thenremoved. Regions other than sections for soldering pads disposed on oneor both surfaces of the multilayer printed wiring board 20 may becovered with a solder resist (not shown) such that the formation ofsolder bridges is prevented. According to the above procedure, themultilayer printed wiring board 20 shown in FIG. 1 can be manufactured.

Second Embodiment

FIG. 3 shows a multilayer printed wiring board 30 according to a secondembodiment of the present invention. That is, the multilayer printedwiring board 30 of this embodiment includes a third resin layer (acoreless layer) 52 including no core material such as a glass cloth. Themultilayer printed wiring board 30 of this embodiment further mayinclude the first via-hole 33-1 and the second via-hole 33-2 similar tothose included in the multilayer printed wiring board 20 of the firstembodiment.

The third resin layer (coreless layer) 52 has substantially the sameconfiguration as those of the first resin layer 26-1 and the secondresin layer 26-2 included in the multilayer printed wiring board 30 ofthis embodiment. The multilayer printed wiring board 30 of thisembodiment is superior in flexibility. Hence, the multilayer printedwiring board 30 of this embodiment can readily absorb the expansion orshrinkage of a wiring board during solder reflow.

-   (1) The multilayer printed wiring board 30 of the second embodiment    is hardly warped by heat during solder reflow; hence, a problem such    as a faulty connection between a semiconductor device and a printed    board hardly occurs.-   (2) Since the multilayer printed wiring board 30 of the second    embodiment is flexible and readily absorbs the expansion of such a    wiring board during solder reflow. Therefore, the multilayer printed    wiring board 30 of the second embodiment absorbs a difference in    thermal expansion coefficient between a semiconductor element and a    printed wiring board 30 of the second embodiment, hence, cracks due    to such a difference are hardly formed.

The second embodiment of the invention is not limited to thisconfiguration. The multilayer printed wiring board 30 of the secondembodiment may include three or more resin layers as required.

A method for manufacturing the multilayer printed wiring board 30 of thesecond embodiment shown in FIG. 3 will now be described with referenceto FIGS. 4A to 4T. If some of steps shown in FIGS. 4A to 4T aresubstantially identical to those shown in FIGS. 2A to 2R, the facts willbe described and the descriptions of the identical steps will beomitted.

As shown in FIG. 4A, a support plate 60 is prepared as startingmaterial. The support plate 60 is preferably made of copper.

As shown in FIG. 4B, plating resist layers 61 are provided on the uppersurface of the support plate 60. The plating resist layers 61 may beformed in such a manner that, for example, a dry film is laminated onthe support plate 60 and then patterned by photolithography.Alternatively a liquid resist may be applied onto the support plate 60by screen printing to form the plating resist layers 61.

As shown in FIG. 4C, conductive films 62 are formed on regions of thesupport plate 60 other than the plating resist films 61 by electrolyticplating using the support plate 60 as a feeder. Before the conductivefilms 62 are formed, a thin film (not shown) including, for example, athin film of Cr and a thin film of Ti may be formed on the upper surfaceof the support plate 60. The thin film may not be etched off by anetchant used to etch the support plate 60 in a step shown in FIG. 4M andtherefore function as etching stoppers.

As shown in FIG. 4D, the plating resist layers 61 formed on the uppersurface of the support plate 60 are removed, such that the conductivefilm 62 is formed. The conductive film has one or more of a land, asignal conductive circuit, a power conductive circuit and/or a grandconductive circuit.

A step of forming a first resin layer 26-1 on the support plate 60 asshown in FIG. 4E is substantially identical to the step shown in FIG.2E. A thickness of the first resin layer may be from 0.02 mm to 0.06 mm.An opening-forming step performed as shown in FIG. 4F is substantiallyidentical to the step shown in FIG. 2F. The opening 26 a-1 in the firstresin layer 26-1 may taper toward the conductive film 62. An electrolessplating step performed as shown in FIG. 4G is substantially identical tothe step shown in FIG. 2G. An electrolytic plating step performed asshown in FIG. 4H is substantially identical to the step shown in FIG.2H. An etching resist-forming step performed as shown in FIG. 4I issubstantially identical to the step shown in FIG. 2I. An etching stepperformed as shown in FIG. 4J is substantially identical to the stepshown in FIG. 2J. An etching resist-removing step performed as shown inFIG. 4K is substantially identical to the step shown in FIG. 2K.

In the stage in FIG. 4K, an upper conductive film 300-1 is formed on thefirst resin layer and the first via-hole 33-1 is formed in the firstresin layer. The first via-hole 33-1 may taper toward the conductivefilm 62. The first via-hole has a bottom surface contacting theconductive film 62 and the bottom surface has a diameter which is from40 μm to 150 μm. A necessary number of resin layers can be formed on thefirst resin layer 26-1 by repeating the steps shown in FIGS. 4E to 4Knecessary times. In this embodiment, these steps are repeated one moretime.

As shown in FIG. 4L, a second resin layer 26-2 having second via-hole33-2 is formed on the first resin layer 26-1 by repeating the stepsshown in FIGS. 4E to 4K once. A thickness of the second resin layer isfrom 0.02 mm to 0.06 mm. An opening for the second via-hole may tapertoward the upper conductive film 300-1. The second via-hole has a bottomsurface contacting the upper conductive film 300-1 and the bottomsurface has a diameter which is from 40 μm to 150 μm. As shown in FIG.4L, an outermost conductive film 300-2 is formed on the second resinlayer.

As shown in FIG. 4M, the support plate 60 is removed by etching. In thestep, the thin film described above with reference to FIG. 4C may beused as an etching stopper.

As shown in FIG. 4N, a third resin layer (coreless layer) 52 is providedon the lower surface of the first resin layer 26-1. The third resinlayer 52 may be formed in such a manner that a semi-cured resin sheet, aresin film or the like is attached to the first resin layer 26-1 andthen heat-cured, or in such a manner that a pre-cured resin is appliedto the first resin layer 26-1 by screen printing and then cured. Athickness of the third resin layer (coreless layer) is from 0.03 mm to0.4 mm.

As shown in FIG. 4O, a third opening 52 a reaching to the conductivefilm on the coreless layer is formed in the third resin layer to form athird via-hole 42. In this step, the conductive film 62 functions asstopper; hence, the opening 52 a reaches to the lower surfaces of theconductive film 62. The opening 52 a in the core less layer may taperstoward the conductive film 62, that is, the opening 52 a may have anupward tapered shape. As described above, the step shown in FIG. 4O issubstantially identical to that shown in FIG. 2M except for the absenceof the copper foils 23.

An electroless plating step performed as shown in FIG. 4P issubstantially identical to the step shown in FIG. 2N. A platingresist-forming step performed as shown in FIG. 4Q is substantiallyidentical to the step shown in FIG. 2O. An electrolytic plating stepperformed as shown in FIG. 4R is substantially identical to the stepshown in FIG. 2P. A plating resist-removing step performed as shown inFIG. 4S is substantially identical to the step shown in FIG. 2Q.

As shown in FIG. 4T, an electroless plating layer 37 is removed by quicketching. A third conductive film 300-3 is formed. In this step, etchingresist layers may be used to cover the third conductive film 300-3and/or the second conductive film 300-2 and/or the second via-hole 33-2.The first via-hole has a bottom surface contacting the conductive film62 on the coreless layer, and the bottom surface of the first via-holehas a diameter which may be from 40 μm to 150 μm. The second via-holehas a bottom surface contacting the conductive film 300-2 on the firstresin layer and the bottom surface of the second via-hole has a diameterwhich may be from 40 μm to 150 μm. The third via-hole has a bottomsurface contacting the conductive film 62 on the coreless layer, and thebottom surface of the third via-hole has a diameter which may be from 60μm to 250 μm. The diameter of the bottom surface of the first and secondvia-holes may be smaller than one of the bottom surface of the corelesslayer.

According to the above procedure, the multilayer printed wiring board 30of the second embodiment shown in FIG. 3 may be manufactured.

[Others]

The embodiments describe above are for exemplification and should not inany way be construed as limitative. The present invention coversmodifications, variations, and substitutes readily made by those skilledin the art.

-   (1) The manufacturing steps described above are current typical    examples. Hence, materials, manufacturing conditions, and the like    used in the manufacturing steps may be varied depending on various    circumstances.-   (2) In the embodiments described above, the semiconductor elements    are mounted on the upper surfaces of the multilayer printed wiring    boards as one example. However, the embodiment of the present    invention cover multilayer printed wiring boards including    semiconductor elements mounted on the lower surfaces or both    surfaces thereof.-   (3) The multilayer printed wiring boards 20 and 30 of the embodiment    shown in FIG. 1 or 3 each include the first and second resin layers    26-1 and 26-2. However, the number of resin layers included in a    multilayer printed wiring board of the embodiment according to the    present invention is not limited to two and may be three or more.    Alternatively, such a multilayer printed wiring board may include a    single resin layer as shown in FIG. 5.-   (4) A method for manufacturing a multilayer printed wiring board of    the embodiment according to the present invention may include a step    of attaching two copper-clad laminates or support plates to each    other with an adhesive such as wax and a step of removing the    copper-clad laminates or the support plates, the removing step being    subsequent to a step of forming portions such as via-holes and    conductive films. The adhesive is not melted or softened at a    process temperature during manufacturing steps but is melted or    softened at a temperature lower than a temperature at which the    multilayer printed wiring board is deteriorated.

Referring to FIG. 5, a multilayer printed wiring board 40 of the thirdembodiment has an insulating layer 220 having an opening. A conductivefilm 23 made of, for example Cu,Au,Ag,Ni,W, is formed on the uppersurface of the insulating layer and is closing one end of the opening ofthe insulating layer. A resin layer 26-1 made of, for example, epoxy,polyimide, or a mixture made of thermosetting resin and thermoplasticresin, is formed on the insulating layer 220 and the conductive film 23and has at least one opening. The opening in the resin layer 26-1 may ormay not be connected to the conductive film 23. A via-hole structure 42is formed in the opening of the insulating layer 220 and has anelectroless plating film 37 and an electroplating film 38. Theelectroless plating film 37 is formed on the surface of the opening ofthe insulating layer and the surface of the conductive film 23, and theelectroplating film 38 is formed on the electroless plating film 37.Another via-hole structure 33-1 is formed in the at least one opening ofthe resin layer 26-1 and has an electroless plating film 28-1 and anelectroplating film 30-1. The electroless plating film 28-1 is formed onthe surface of the opening of the resin layer and the electroplatingfilm 30-1 is formed on the electroless plating film 28-1. Theelectroless plating film 28-1 of the via-hole structure 33-1 may beformed on the surface of the conductive film. Thus, on the upper surfaceof the conductive film, one via-hole structure having an electrolessplating film and an electroplating film in this order is formed, and onthe lower surface of the conductive film, the other via-hole structurehaving an electroless plating film and an electroplating film in thisorder is formed. By providing such a structure, stress due to thoseplating films on the multilayered printed wiring board is reducedsignificantly. The insulating layer 220 may be a core layer or acoreless layer. The core layer has a resin and a core material such as aglass cloth or a glass fiber, and the core layer may be a single-side ora double-side copper-clad laminate. For example, the core layer may bemade of a glass cloth base epoxy-resin impregnated copper-clad laminate,a glass-based material impregnated with a bismaleimide triazine resin, alaminate including a glass-based material impregnated with apolyphenylene ether resin, or a laminate including a glass-basedmaterial impregnated with a polyimide resin. The coreless layer has aresin layer without the core material. For example, the coreless layermay be made of a resin layer, such as epoxy, or polyimide, without thecore layer. The multilayer printed wiring board 40 of the thirdembodiment may be manufactured by the steps shown in FIGS. 2A to 2Rwithout repeating the steps shown in FIG. 2E to 2K. As another method,the multilayer printed wiring board 40 of the third embodiment may bemanufactured by the steps shown in FIGS. 4A to 4T without repeating thesteps shown in FIG. 4E to 4K. The via-hole structures 42, 33-1 may tapertoward the conductive film 23. A thickness of the resin layer 26-1 maybe from 0.02 mm to 0.06 mm. A thickness of the insulating layer 220 maybe from 0.03 mm to 0.4 mm. The thickness of the insulating layer may beequal to or thicker than one of the resin layers. The via-hole structure33-1 has a bottom surface contacting the conductive film 23 on theinsulating layer and the bottom surface of the via-hole structure 33-1has a diameter which may be from 40 μm to 150 μm. The via-hole structure42 has a bottom surface contacting the conductive film 62 on thecoreless layer, and the bottom surface of the via-hole structure 42 hasa diameter which may be from 60 μm to 250 μm. The diameter of the bottomsurface of the via-hole structure 42 may be larger than one of thebottom surface of via-hole structure 33-1. The via-hole structures 42,33-1 may taper toward the conductive film 23.

Specifically, in the method of the first embodiment, the steps shown inFIGS. 2A to 2L may be applied to each of two copper-clad laminates 21including copper foils 23 attached to each other such that the copperfoils 23 are fixed to each other with an adhesive. In the method of thesecond embodiment as well as the method of the first embodiment, thesteps shown in FIGS. 4A to 4L may be applied to each of two supportplates or copper plates 60 attached to each other with an adhesive.Then, two printed boards obtained are separated from each other andseparately processed in subsequent steps.

According to this procedure, since the two copper-clad laminates 21 orsupport plates 60 are fixed to each other with such an adhesive, the twocopper-clad laminates or support plates can be processed into the twoprinted boards simultaneously or successively, whereby two multilayerprinted wiring boards may be manufactured at once. The two multilayerprinted wiring boards fixed to each other are heated to a temperature atwhich the adhesive is melted or softened, whereby the two multilayerprinted wiring boards are separated from each other. The resulting twomultilayer printed wiring boards are then separately processed insubsequent steps.

The scope of the present invention is defined by the appended claims.

1. A method for manufacturing a multilayer printed wiring board,comprising: preparing a single- or double-sided copper-clad laminate;forming a conductive film on an upper surface of the copper-cladlaminate; forming a resin layer on the upper surface of the copper-cladlaminate; forming a opening for via-hole in the resin layer, forming thevia-hole in the resin layer; forming a opening for via-holes in thecopper-clad laminate; and forming the via-hole in the copper-clad,wherein the via-hole formed in the resin layer is open in the directionopposite to the direction in which the via-hole formed in thecopper-clad laminate is open.
 2. The method according to claim 1,wherein the via-hole formed in the resin layer taper toward theconductive film, and the via-hole formed in the copper-clad laminatetapers toward the conductive film.
 3. The method according to claim 1,wherein the copper-clad laminate includes a glass fabric impregnatedwith an epoxy resin.
 4. The method according to claim 1, furthercomprising: forming another resin layer on the resin layer; forminganother opening for a via-hole in the another resin layer; and forminganother via-hole in the another resin layer.
 5. The method according toclaim 1, wherein the via-holes are filled with a conductor by platingprocess.
 6. The method according to claim 1, further comprising:attaching a single or double-side copper-clad laminate to each otherwith an adhesive; and separating the two copper-clad laminates bymelting or softening the adhesive.
 7. A method for manufacturing amultilayer printed wiring board comprising: preparing a support plate;forming a conductive film on the support plate; forming a first resinlayer on the upper surface of the support plate; forming a first openingfor a first via-hole in the first resin layer; forming the firstvia-hole in the first resin layer; forming a second resin layer on theupper surface of the first resin layer; forming a second opening for asecond via-hole in the second resin layer; forming the second via-holein the second resin layer; removing the support plate; forming acoreless layer on the lower surface of the first resin layer; forming athird opening for a third via-hole in the coreless layer, and formingthe third via-hole in the coreless layer, wherein the first opening andthe second opening are open in the direction opposite to the directionin which the third opening is open.
 8. The method according to claim 7,wherein the via-holes formed in the first and second resin layersbroaden upward and taper downward and the via-hole formed in thecoreless layer tapers upward and broadens downward.
 9. The methodaccording to claim 7, wherein the each via-hole is filled with aconductor by plating process.
 10. The method according to claim 7,further comprising: attaching two support plates to each other with anadhesive; and separating the two support plates by melting or softeningthe adhesive.